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IS62LV12816L
IS62LV12816L
128K x 16 CMOS STATIC RAM
ISSI
DESCRIPTION
ISSI(R)
(R)
ADVANCE INFORMATION AUGUST 1998
1
FEATURES
* High-speed access time: 70, 100, and 120 ns * CMOS low power operation - 120 mW (typical) operating - 6 W (typical) CMOS standby * TTL compatible interface levels * Single 3V 10% VCC power supply * Fully static operation: no clock or refresh required * Three state outputs * Data control for upper and lower bytes * Industrial temperature available * Available in the 44-pin TSOP (Type II) and 48-pin mini BGA
The ISSI IS62LV12816L is a high-speed, 2,097,152-bit static RAM organized as 131,072 words by 16 bits. It is fabricated using ISSI's high-performance CMOS technology. This highly reliable process coupled with innovative circuit design techniques, yields high-performance and low power consumption devices. When CE is HIGH (deselected), the device assumes a standby mode at which the power dissipation can be reduced down with CMOS input levels. Easy memory expansion is provided by using Chip Enable and Output Enable inputs, CE and OE. The active LOW Write Enable (WE) controls both writing and reading of the memory. A data byte allows Upper Byte (UB) and Lower Byte (LB) access. The IS62LV12816L is packaged in the JEDEC standard 44-pin TSOP (Type II) and 48-pin mini BGA.
2 3 4 5 6
FUNCTIONAL BLOCK DIAGRAM
7
A0-A16 DECODER 128K x 16 MEMORY ARRAY
8 9
VCC GND I/O0-I/O7 Lower Byte I/O8-I/O15 Upper Byte I/O DATA CIRCUIT
COLUMN I/O
10 11
CE OE WE UB LB
The specification contains ADVANCE INFORMATION. ISSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any errors which may appear in this publication. (c) Copyright 1998, Integrated Silicon Solution, Inc.
CONTROL CIRCUIT
12
Integrated Silicon Solution, Inc.
ADVANCE INFORMATION SR002-0C 08/20/98
1
IS62LV12816L
PIN CONFIGURATIONS 44-Pin TSOP (Type II)
A4 A3 A2 A1 A0 CE I/O0 I/O1 I/O2 I/O3 Vcc GND I/O4 I/O5 I/O6 I/O7 WE A16 A15 A14 A13 A12 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 A5 A6 A7 OE UB LB I/O15 I/O14 I/O13 I/O12 GND Vcc I/O11 I/O10 I/O9 I/O8 NC A8 A9 A10 A11 NC
ISSI
48-Pin mini BGA
1 A B C D E F G H
LB I/O8 I/O9 GND Vcc I/O14 I/O15 NC
(R)
2
OE UB I/O10 I/O11 I/O12 I/O13 NC A8
3
A0 A3 A5 NC NC A14 A12 A9
4
A1 A4 A6 A7 A16 A15 A13 A10
5
A2 CE I/O1 I/O3 I/O4 I/O5 WE A11
6
N/C I/O0 I/O2 Vcc GND I/O6 I/O7 NC
PIN DESCRIPTIONS
A0-A16 I/O0-I/O15 Address Inputs Data Inputs/Outputs Chip Enable Input Output Enable Input Write Enable Input
LB UB
NC Vcc GND
Lower-byte Control (I/O0-I/O7) Upper-byte Control (I/O8-I/O15) No Connection Power Ground
CE OE WE
TRUTH TABLE
Mode Not Selected Output Disabled Read
WE
X H X H H H L L L
CE
H L L L L L L L L
OE
X H X L L L X X X
LB
X X H L H L L H L
UB
X X H H L L H L L
I/O PIN I/O0-I/O7 I/O8-I/O15 High-Z High-Z High-Z DOUT High-Z DOUT DIN High-Z DIN High-Z High-Z High-Z High-Z DOUT DOUT High-Z DIN DIN
Vcc Current ISB1, ISB2 ICC ICC
Write
ICC
2
Integrated Silicon Solution, Inc.
ADVANCE INFORMATION SR002-0C 08/20/98
IS62LV12816L
OPERATING RANGE
Range Commercial Industrial Ambient Temperature 0C to +70C -40C to +85C VCC 3.0V 10% 3.0V 10%
ISSI
(R)
1
Unit V C V C W
ABSOLUTE MAXIMUM RATINGS(1)
Symbol VTERM TBIAS VCC TSTG PT Parameter Terminal Voltage with Respect to GND Temperature Under Bias Vcc Related to GND Storage Temperature Power Dissipation Value -0.5 to Vcc+0.5 -40 to +85 -0.3 to +4.0 -65 to +150 1.0
2 3 4 5
Note: 1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
DC ELECTRICAL CHARACTERISTICS (Over Operating Range)
Symbol VOH VOL VIH VIL(1) ILI ILO Parameter Output HIGH Voltage Output LOW Voltage Input HIGH Voltage Input LOW Voltage Input Leakage Output Leakage GND VIN VCC GND VOUT VCC, Outputs Disabled Test Conditions VCC = Min., IOH = -1 mA VCC = Min., IOL = 2.1 mA Min. 2.0 -- 2.2 -0.2 -1 -1 Max. -- 0.4 VCC + 0.2 0.4 1 1 Unit V V V V A A
6 7 8 9
Notes: 1. VIL (min.) = -2.0V for pulse width less than 10 ns.
POWER SUPPLY CHARACTERISTICS(1) (Over Operating Range)
Symbol Parameter ICC ISB1 Vcc Dynamic Operating Supply Current TTL Standby Current (TTL Inputs) CMOS Standby Current (CMOS Inputs) Test Conditions VCC = Max., IOUT = 0 mA, f = fMAX VCC = Max., VIN = VIH or VIL CE VIH , f = 0 Com. Ind. Com. Ind. Com. Ind. -70 Min. Max. -- -- -- -- -- -- 40 60 0.4 1.0 15 25 -100 Min. Max. -- -- -- -- -- -- 30 50 0.4 1.0 15 25 -120 Min. Max. -- -- -- -- -- -- 20 40 0.4 1.0 15 25 Unit mA mA
10 11 12
ISB2
CE VCC - 0.2V,
VCC = Max.,
A
VIN VCC - 0.2V, or VIN 0.2V, f = 0
Note: 1. At f = fMAX, address and data inputs are cycling at the maximum frequency, f = 0 means no input lines change.
Integrated Silicon Solution, Inc.
ADVANCE INFORMATION SR002-0C 08/20/98
3
IS62LV12816L
CAPACITANCE(1)
Symbol CIN COUT Parameter Input Capacitance Input/Output Capacitance Conditions VIN = 0V VOUT = 0V Max. 6 8 Unit pF pF
ISSI
(R)
Note: 1. Tested initially and after any design or process changes that may affect these parameters.
AC TEST CONDITIONS
Parameter Input Pulse Level Input Rise and Fall Times Input and Output Timing and Reference Level Output Load Unit 0.4V to 2.2V 5 ns 1.5V See Figures 1 and 2
AC TEST LOADS
3070 2.8V 2.8V 3070
OUTPUT 100 pF Including jig and scope
Figure 1
OUTPUT 3150 5 pF Including jig and scope
Figure 2
3150
4
Integrated Silicon Solution, Inc.
ADVANCE INFORMATION SR002-0C 08/20/98
IS62LV12816L
READ CYCLE SWITCHING CHARACTERISTICS(1) (Over Operating Range)
Symbol Parameter Read Cycle Time Address Access Time Output Hold Time Min. 70 -- 10 -- -- -- 5 0 10 -- 0 0 -70 Max. -- 70 -- 70 35 25 -- 25 -- 35 25 -- -100 Min. Max. 100 -- 15 -- -- -- 5 0 10 -- 0 0 -- 100 -- 100 50 30 -- 30 -- 50 35 -- -120 Min. Max. 120 -- 15 -- -- 0 5 0 10 -- 0 0 -- 120 -- 120 60 40 -- 40 -- 60 50 -- Unit ns ns ns ns ns ns ns ns ns ns ns ns
ISSI
(R)
tRC tAA tOHA tACE tDOE tHZOE(2) tLZOE
(2) (2)
1 2 3 4 5 6 7 8
tHZCE tBA tHZB tLZB
tLZCE(2)
CE Access Time OE Access Time OE to High-Z Output OE to Low-Z Output CE to High-Z Output CE to Low-Z Output LB, UB Access Time LB, UB to High-Z Output LB, UB to Low-Z Output
Notes: 1. Test conditions assume signal transition times of 5 ns or less, timing reference levels of 1.5V, input pulse levels of 0.4 to 2.2V and output loading specified in Figure 1. 2. Tested with the load in Figure 2. Transition is measured 500 mV from steady-state voltage. Not 100% tested.
AC WAVEFORMS READ CYCLE NO. 1(1,2) (Address Controlled) (CE = OE = VIL, UB or LB = VIL)
tRC
ADDRESS
tAA tOHA tOHA
DATA VALID
9 10 11 12
DOUT
PREVIOUS DATA VALID
Integrated Silicon Solution, Inc.
ADVANCE INFORMATION SR002-0C 08/20/98
5
IS62LV12816L
AC WAVEFORMS READ CYCLE NO. 2(1,3)
tRC
ISSI
(R)
ADDRESS
tAA tOHA
OE
tDOE tHZOE
CE
tLZCE
tLZOE tACE tHZCE
LB, UB
tBA tHZB
DATA VALID
DOUT
HIGH-Z
tLZB
Notes: 1. WE is HIGH for a Read Cycle. 2. The device is continuously selected. OE, CE, UB, or LB = VIL. 3. Address is valid prior to or coincident with CE LOW transition.
WRITE CYCLE SWITCHING CHARACTERISTICS(1,2) (Over Operating Range)
Symbol Parameter Write Cycle Time Min. 70 65 65 0 0 60 60 30 0 -- 5 -70 Max. -- -- -- -- -- -- -- -- -- 30 -- -100 Min. Max. 100 80 80 0 0 80 80 40 0 -- 5 -- -- -- -- -- -- -- -- -- 40 -- -120 Min. Max. 120 100 100 0 0 100 100 50 0 -- 5 -- -- -- -- -- -- -- -- -- 50 -- Unit ns ns ns ns ns ns ns ns ns ns ns
tWC tSCE tAW tHA tSA tPWB tPWE tSD tHD tHZWE(3) tLZWE(3)
CE to Write End
Address Setup Time to Write End Address Hold from Write End Address Setup Time
LB, UB Valid to End of Write WE Pulse Width
Data Setup to Write End Data Hold from Write End
WE LOW to High-Z Output WE HIGH to Low-Z Output
Notes: 1. Test conditions assume signal transition times of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0.4V to 2.2V and output loading specified in Figure 1. 2. The internal write time is defined by the overlap of CE LOW and UB or LB, and WE LOW. All signals must be in valid states to initiate a Write, but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the rising or falling edge of the signal that terminates the write. 3. Tested with the load in Figure 2. Transition is measured 500 mV from steady-state voltage. Not 100% tested.
6
Integrated Silicon Solution, Inc.
ADVANCE INFORMATION SR002-0C 08/20/98
IS62LV12816L
AC WAVEFORMS WRITE CYCLE NO. 1(1,2) (WE Controlled)
tWC
ISSI
(R)
1
tHA
ADDRESS
tSCE
2 3
CE
tPWB
LB, UB
tAW tPWE
WE
tSA
4 5
tHD
WRITE(1)
tSD
DIN
tHZWE tLZWE
UNDEFINED HIGH-Z UNDEFINED HIGH-Z
6 7 8 9 10 11 12
DOUT
Notes: 1. WRITE is an internally generated signal asserted during an overlap of the LOW states on the CE and WE inputs and at least one of the LB and UB inputs being in the LOW state. 2. WRITE = (CE) [ (LB) = (UB) ] (WE).
Integrated Silicon Solution, Inc.
ADVANCE INFORMATION SR002-0C 08/20/98
7
IS62LV12816L
DATA RETENTION SWITCHING CHARACTERISTICS
Symbol Parameter Vcc for Data Retention Data Retention Current Data Retention Setup Time Recovery Time Test Condition See Data Retention Waveform Vcc = 2.0V, CE Vcc - 0.2V See Data Retention Waveform See Data Retention Waveform Min. 1.5 -- 0 Max. 3.3 15 -- -- Unit V A ns ns
ISSI
(R)
VDR
IDR
tSDR tRDR
tRC
DATA RETENTION WAVEFORM (CE Controlled)
tSDR VCC 2.3V Data Retention Mode tRDR
2.0V
VDR CE VCC - 0.2V
CE GND
8
Integrated Silicon Solution, Inc.
ADVANCE INFORMATION SR002-0C 08/20/98
IS62LV12816L
ORDERING INFORMATION Commercial Range: 0C to +70C
Speed (ns) 70 70 100 100 120 120 Order Part No. IS62LV12816L-70T IS62LV12816L-70B IS62LV12816L-100T IS62LV12816L-100B IS62LV12816L-120T IS62LV12816L-120B Package TSOP (Type II) Mini BGA TSOP (Type II) Mini BGA TSOP (Type II) Mini BGA
ISSI
(R)
1 2 3 4 5 6 7 8 9 10
Industrial Range: -40C to +85C
Speed (ns) 70 70 100 100 120 120 Order Part No. IS62LV12816L-70TI IS62LV12816L-70BI Package TSOP (Type II) Mini BGA
IS62LV12816L-100TI TSOP (Type II) IS62LV12816L-100BI Mini BGA IS62LV12816L-120TI TSOP (Type II) IS62LV12816L-120BI Mini BGA
ISSI
(R)
Integrated Silicon Solution, Inc.
2231 Lawson Lane Santa Clara, CA 95054 Fax: (408) 588-0806 Toll Free: 1-800-379-4774 email: sales@issi.com http://www.issi.com
Integrated Silicon Solution, Inc.
ADVANCE INFORMATION SR002-0C 08/20/98
11 12
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